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BiCSL — Bitbang Computer Science Lab

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Papers, datasets, software and talks from the lab. Every record has a persistent ID, downloadable files with checksums, version history and ready-made citations.

3 records for “IR”

Nov 3, 2026PreprintOpen accessv1.0

Implementing Logic Gates with Acid–Base Neutralization: Focusing on the Reproduction of the XOR Gate

Jeonghoon Bang

This study began from the observation that litmus paper takes one of two colors, red in acid and blue in base, much like the 0 and 1 of binary numbers, and asked whether acid–base neutralization can perform logic operations. We built an ion-counting model with two rules, that H⁺ and OH⁻ react one to one to form water and that the current of a solution is proportional to the number of remaining ions, and computed it with a Python program and a web simulator. With litmus, NOT, OR, NOR, AND and NAND gates could be built, but an XOR gate never appeared while the amount of base in the background solution was varied from 0 to 3 units. Litmus shows only which kind of ion remains, and that kind changes in one direction only as acid is added. This is the same structure that prevents a single-layer perceptron from computing XOR. Reading the same reaction by electric current reveals how many ions remain. With sulfuric acid and barium hydroxide as inputs, the ions disappear as water and precipitate when the two inputs are equal, so the bulb behaved as an XOR gate. Hydrochloric acid and sodium hydroxide, in contrast, leave Na⁺ and Cl⁻ after neutralization and behaved as an OR gate. Finally, when two XOR beakers were chained, pouring the first solution directly into the second gave a wrong answer in one of eight cases, while signal restoration, reading only the result and adding a fresh solution, gave correct answers in all cases. This is the role shared by transistors, activation functions in neural networks, and action potentials in neurons.

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Sep 3, 2026Technical reportOpen accessv1.0

Comparison of the von Neumann Bottleneck and the Efficiency of the Systolic Array Architecture

Jeonghoon Bang, Seojun Kim, Yoongi Hong, Yesung Choi

This research directly implemented the sequential memory access approach of the Von Neumann architecture and the parallel processing approach of the systolic array architecture using five Arduino Nano-compatible boards, comparing the processing time and the number of data movements for the identical matrix multiplication operation. The control group simulated the Von Neumann access pattern through sequential access routed via global bus variables, while the experimental group implemented an output-stationary (OS) data flow by configuring four processing elements (PEs) in a $2 \times 2$ grid. The internal dimension $K$ of the matrices was varied to 2, 4, 6, and 8, with measurements repeated at least 5 times under each condition. The measurement results showed that the logical number of data element movements was 25% lower for the systolic array across all intervals ($8K$ versus $6K$). However, the processing time was 295 to 326 times slower. The slope ratio of the two regression equations was 313.2, and the intercept was also greater for the grid structure, meaning no break-even point appeared even as $K$ was increased. The cause lay in the difference in cost per data movement: while an in-chip variable access took 3.23 µs, inter-board GPIO communication took 1,346.9 µs—making it approximately 417 times more expensive. Reducing the number of movements by 25% was insufficient to offset this unit cost difference. These results demonstrate that the data reuse principle of the systolic array operated effectively even in this experimental environment. At the same time, the experiment confirmed the prerequisite that for this principle to translate into a performance advantage, communication costs between PEs must be sufficiently lower than memory access costs. The performance of a systolic array is ultimately determined by the physical integration density between PEs. This inversely illustrates the rationale behind the design choice of actual TPUs to integrate hundreds of PEs within a single chip.

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Jul 6, 2026Conference paperOpen accessv1.0

Electrical signals in neurons and artificial neural networks

Jeonghoon Bang, Mingyu Cho

This report analyzes the process by which the core technology underlying the mechanism of electrical signal transmission in human nerve cells (neurons) was developed and advanced into artificial neural networks. First, this report explains the structure of neurons, the definition of membrane potential, and the process and principles behind the generation of action potentials, and defines how these signals enable information to travel from one neuron to another. In particular, it clarifies that not all stimuli to a neuron result in a signal; rather, the concept of a stimulus exceeding a certain threshold is necessary, and this is summarized through the “all-or-nothing” principle. To analyze how electrical signals—which are merely simple neurological signals—evolved into artificial neural networks, this study defined the concept of weights through perceptron theory, as well as multi-perceptrons and the backpropagation algorithm. It then described the progression to deep learning in artificial intelligence, supported by scientific facts, and demonstrated how stimuli exceeding a neuron’s threshold are applied to modern AI technology through the use of activation functions such as the sigmoid, ReLU, and Softmax to demonstrate how stimuli exceeding a neuron’s threshold are applied in modern AI technology. Finally, the paper examined the areas of application for artificial neural networks and summarized, based on the development of core AI principles, how they are integrated into fields such as healthcare, autonomous vehicles, image recognition, weather forecasting services, and AI chatbots. Through the advancements in deep learning and AI—enhanced by development based on the emulation of human neurons—the importance and value of the convergent development of life sciences and engineering were confirmed.

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